India's Silicon Dawn: DHRUV64 and the Architecture of Sovereign Computing
C-DAC has unveiled India's first fully indigenous 1 GHz, 64-bit dual-core processor — fabricated on 28 nm, built on RISC-V, and owned entirely by Indian institutions. This is not a research prototype. It is the start of a processor dynasty.
In December 2025, India crossed a frontier it had been quietly approaching for years. The Centre for Development of Advanced Computing unveiled DHRUV64 — the country's first fully indigenous 1 GHz, 64-bit dual-core microprocessor. It runs on open architecture, it is owned entirely by Indian institutions, and it carries implications that stretch well beyond its clock speed.
There is a particular kind of invisibility that hides in plain sight. Every smartphone call routed through an Indian telecom tower, every transaction cleared by a domestic bank's server, every navigational command issued to a satellite built in Bengaluru — all of these events are powered by chips that India, until very recently, did not design or own. The processor architectures powering critical national infrastructure have been licensed from abroad for decades: x86 cores from Intel and AMD, ARM designs from a British IP firm, and MIPS derivatives scattered through embedded systems across industry.
DHRUV64 changes that equation at the most foundational level. Developed by C-DAC under the Ministry of Electronics and Information Technology's Microprocessor Development Programme, it is formally designated VEGA AS2161. It is the third processor to reach fabrication under India's Digital India RISC-V programme — and the most advanced by a significant margin.
Why Silicon Has Hit a Sovereignty Wall
Benchmarks tell one story. Geopolitics tells another. DHRUV64 will not outsprint a Qualcomm Snapdragon in a smartphone, and nobody designing it expected it to. What the chip delivers is something harder to quantify but far more consequential for a nation-state: freedom from architectural dependency.
Consider what it means for a country's defence systems, power grids, or satellite platforms to run on processors owned by another country's corporations. It means the processor manufacturer can, in theory, comply with an export ban. It means a hardware backdoor discovered years after deployment might not be patchable if the original IP holder does not cooperate. It means long-term supply chain risk accumulates silently inside the most sensitive infrastructure imaginable.
The United States demonstrated exactly how this works when it placed export controls on advanced semiconductors bound for China. The scramble that followed — Chinese firms racing to develop domestic alternatives at enormous cost — illustrated with unusual clarity what technological dependency looks like when geopolitical conditions change. India, which maintains multi-alignment in its foreign policy, has every strategic reason to own its own silicon rather than depend on any single power's manufacturing or licensing infrastructure.
Moore's Law is slowing. But India's dependency on foreign processor architectures is a problem that silicon alone cannot solve — it requires ownership. DHRUV64 is India's declaration that it will design its own future, not license it. — Libin T.T., Scientist F, C-DAC Thiruvananthapuram (via EE Times, December 2025)
The RISC-V choice is central to this logic. Unlike ARM, which charges royalties and controls the architecture through a licensing model, or x86, which is exclusively held by Intel and AMD, RISC-V is governed by an open international standards body. No single country or company can revoke access, restrict modifications, or place export controls on the architecture itself. For India, this means DHRUV64's design can be freely extended, modified for classified defence requirements, shared with domestic universities, and adapted for space-grade use — without seeking anyone's permission abroad.
Inside the Chip: What DHRUV64 Actually Is
DHRUV64 runs at 1 GHz across two 64-bit RISC-V cores. It integrates a DDR4 memory interface with a quoted 75.4 GB/s memory interconnect bandwidth, 128 KB of on-chip SRAM, a multi-level cache hierarchy, a memory management unit, and a low-latency vectored interrupt controller that supports mixed real-time and Linux environments simultaneously. It boots Linux. It exposes standard RISC-V toolchain support with JTAG debug, Eclipse and GDB compatibility, and AXI-compliant interfaces for broader system integration.
Libin T.T., Scientist F at C-DAC's Thiruvananthapuram centre, described DHRUV64 as a deliberate intermediate milestone rather than a technological leap. The design philosophy was to progress in controlled, manageable steps — from low-frequency 32-bit microcontrollers into the gigahertz application-processor range — without introducing too many variables at once. "That would have been an exponential jump," he said. "So, we treated DHRUV64 as an intermediate milestone."
Some IP blocks — notably the DDR memory interface — were licensed as minimum essential components. The overall system architecture, the processor core implementation, and the SoC integration are entirely indigenous. The chip was taped out on a 28 nm process at an external foundry, most likely in Taiwan, since India's domestic Semiconductor Laboratory (SCL) in Mohali currently operates at 180 nm. That changes before the end of 2026.
India's Import Problem: The Numbers Behind the Strategy
The strategic urgency behind DHRUV64 is not theoretical. India consumes an estimated 20 percent of global microprocessor output. Semiconductor imports reached nearly USD 24 billion in 2024. The domestic semiconductor market, valued at approximately USD 45 billion in 2025, is growing at a 13 percent compound annual rate and is projected to reach USD 100–110 billion by 2030. The overwhelming majority of chips powering Indian devices and critical systems are designed and manufactured outside the country.
The Lineage: India's Indigenous Processor Journey
DHRUV64 did not emerge from a vacuum. It is the most mature expression of a processor development tradition that India has been quietly building since 2018. Understanding the lineage makes the achievement clearer and the trajectory more legible.
Comparing India's Indigenous Processors
| Processor | Developer | Year | Architecture | Bit Width | Process Node | Fabrication Site | Primary Domain | Status |
|---|---|---|---|---|---|---|---|---|
| SHAKTI | IIT Madras | 2018 | RISC-V | 32/64-bit | 180 nm | SCL Mohali / TSMC | Defence / Space / Strategic | Active |
| AJIT | IIT Bombay | 2018 | Custom ISA | 32-bit | 180 nm | SCL Mohali | Industrial / Robotics | Active |
| THEJAS32 | C-DAC | 2022 | RISC-V | 32-bit | 180 nm | Silterra, Malaysia | Embedded / IoT | Production |
| THEJAS64 | C-DAC | 2025 | RISC-V | 64-bit | 180 nm | SCL Mohali (India) | Industrial Automation | Production |
| VIKRAM | ISRO / SCL | 2025 | RISC-V | 32-bit | 180 nm | SCL Mohali (India) | Space / Navigation | Active |
| DHRUV64 | C-DAC | 2025 | RISC-V (RV64GC) | 64-bit Dual-core | 28 nm | External (Taiwan) | 5G / IoT / Auto / Defence | Validation |
| Dhanush64 | C-DAC | 2026+ | RISC-V (SoC) | 64-bit | TBD | TBD | Commercial / Strategic | Development |
| Dhanush64+ | C-DAC | 2026+ | RISC-V (SoC+) | 64-bit | TBD | TBD | Advanced Compute / AI-edge | Development |
The Institutional Framework Driving the Ecosystem
DHRUV64 is not the output of a single laboratory sprint. It is the product of a coordinated institutional architecture assembled over several years — combining policy, capital, training, and research under a unified semiconductor strategy. Six major programmes converge to support it, underpinned by ₹1.60 lakh crore in committed investments across ten approved projects in six states.
| Programme | Launched | Lead Body | Focus Area | Scale / Outlay |
|---|---|---|---|---|
| India Semiconductor Mission (ISM) | 2021 | MeitY | Fab investment, ATMP, design ecosystem | ₹1.60 lakh crore across 10 projects, 6 states |
| ISM 2.0 (Union Budget 2026–27) | 2026 | MeitY | Equipment mfg., full-stack design, IP building | ₹1 trillion fund proposed |
| Digital India RISC-V (DIR-V) | Apr 2022 | C-DAC / MeitY | Indigenous RISC-V processor development | 3 chips taped out: THEJAS32, THEJAS64, DHRUV64 |
| Chips to Startup (C2S) | 2022 | MeitY | Semiconductor talent pipeline | 113 institutions; 85,000 professionals; ₹250 crore |
| Design Linked Incentive (DLI) | 2021 | MeitY / ISM | Fabless chip design startups | Financial support for 100 domestic chip companies |
| INUP-i2i | Ongoing | DST / IITs | Nanofabrication access for researchers | Cleanroom and device access at national institutions |
Sitting atop this policy framework is rapidly maturing physical infrastructure. Micron's OSAT facility in Sanand, Gujarat began Phase 1 operations in mid-2025. CG Semi — India's first full-service outsourced assembly and test provider — was inaugurated on 28 August 2025, with capacity for 0.5 million chips per day scaling toward 14.5 million. Kaynes Semicon's Sanand facility launched on 31 March 2026 with 6 million chip-per-day capacity. Most significantly, Tata Electronics' planned fabrication facility at Dholera, Gujarat — partnered with Taiwan's PSMC — received SEZ notification on 9 April 2026. When India's 28 nm fab comes online, the Dhanush generation of processors may be fabricated on Indian soil.
What DHRUV64 Unlocks for the Ecosystem
Beyond strategic security, DHRUV64 carries practical value for India's civilian technology community. India is home to roughly 20 percent of the world's chip design engineers — an extraordinary talent pool that has historically worked primarily on designs owned by foreign companies. DHRUV64 gives that talent something it has never had before: a real, homegrown, general-purpose processor to build on, extend, and ship products around.
| Stakeholder Segment | Benefit from DHRUV64 | Example Applications |
|---|---|---|
| Defence & Space | Full RTL ownership; no export control risk; fully auditable logic | Radar signal processing, satellite onboard compute, EW systems |
| 5G Infrastructure | Trusted domestic processor for base station edge compute | RAN controllers, network function virtualisation units |
| Automotive / EV | Embedded Linux-capable SoC for ADAS and telematics | Vehicle control modules, OBD interfaces, connected car platforms |
| Industrial Automation | Real-time + Linux capable; vectored interrupt controller | PLC replacements, robotics controllers, smart grid edge nodes |
| IoT & Edge Computing | 64-bit capable, Linux-bootable, compact SoC form factor | Smart meters, agricultural sensors, medical device platforms |
| Startups & Academia | Open RISC-V — no licensing barriers, standard developer toolchain | Prototype SoCs, custom ASIC derivatives, research platforms |
Honest Limitations: What DHRUV64 Is Not
Intellectual honesty demands a clear account of what DHRUV64 does not yet achieve. At 1 GHz on a 28 nm process, it lags behind contemporary smartphone SoCs by a decade of performance density. It lacks integrated GPU functionality, AI inference accelerators, and the deep software ecosystems — toolchains, drivers, certified middleware — that mature platforms like ARM Cortex-A or commercial RISC-V alternatives from SiFive already offer to engineers today.
As Libin T.T. acknowledged directly: "Indigenous will not always sell. Engineers will choose a chip based on technical reasons." The commercial adoption challenge is real. Any electronics manufacturer comparing DHRUV64 against a mature ARM SoC will find the incumbent wins on software support, peripheral variety, and developer community size. C-DAC has stated that evaluation units are not yet available, and broader access is expected only after interface validation concludes.
India vs the World: The Race for Chip Sovereignty
India's programme is unfolding inside a global contest in which major powers are committing unprecedented capital to secure domestic semiconductor capability. The United States enacted the CHIPS and Science Act with USD 52.7 billion. China's National IC Industry Investment Fund exceeds USD 47 billion, targeting 70 percent self-sufficiency and 30 percent of global foundry capacity by 2030. The European Union's Chips Act targets 20 percent of global production by 2030.
India already holds nearly 20 percent of the world's chip design engineers. DHRUV64 gives that extraordinary talent something it has never had before: a real, homegrown processor to build around — without any foreign IP holder's permission required. — BusinessToday, citing MeitY / C-DAC programme communications, December 2025
| Country | Key Programme | Investment / Outlay | Primary Focus | Indigenous Chip Milestone |
|---|---|---|---|---|
| USA | CHIPS and Science Act | USD 52.7 billion | Revive domestic mfg.; design leadership | Leads global design revenue (~52%) |
| China | National IC Fund + Made in China 2025 | USD 47+ billion | Full vertical integration; self-sufficiency | HiSilicon Kirin; Zhaoxin; CXMT DRAM |
| EU | European Chips Act | €43 billion | 20% global production share by 2030 | Limited — still dependent on external fabs |
| Japan | Rapidus Programme | ~$13 billion (govt. share) | 2 nm domestic fab by 2027 | Renesas automotive SoCs; Fujitsu HPC chips |
| India | ISM + DIR-V + ISM 2.0 | ₹1.60 lakh crore + ₹1 trillion proposed | Design sovereignty, OSAT, then advanced fabs | DHRUV64 — first indigenous 64-bit dual-core |
From DHRUV64 to Dhanush: The Continuity Thesis
Perhaps the most important thing about DHRUV64 is not the chip itself — it is the roadmap it anchors. C-DAC has publicly confirmed that work on next-generation Dhanush64 and Dhanush64+ SoC variants is already underway. The DIR-V roadmap calls for progressively more capable processors, deeper SoC integration, and eventually AI inference accelerators and graphics capability — making Indian-designed processors competitive not just in strategic embedded applications, but in edge AI and industrial compute markets globally.
The logic mirrors the philosophy that once drove India's supercomputing ambitions. PARAM 8000 was not born into a vacuum — it came from a national decision to own compute rather than purchase it, to build institutional memory rather than rely on vendor support cycles. DHRUV64 carries the same philosophical DNA, expressed at the level of the chip itself. It is not the finish line. It is the infrastructure on which future finish lines are built.
By the end of 2026, India will have domestic OSAT facilities operational in Gujarat, a 28 nm fab coming online at Dholera, a processor ecosystem spanning defence, space, industrial, IoT, and consumer applications, and a trained workforce of tens of thousands of semiconductor engineers. The strategic question is not whether DHRUV64 can displace ARM in smartphones. The question is whether India can sustain and accelerate the trajectory it represents — and the current evidence across institutional, financial, and physical infrastructure suggests the answer is yes.
The transistor was invented in 1947. It took two decades to become the foundation of modern computing. Every transformative computing transition has followed the same arc: demonstrated in a lab, dismissed as impractical, and then suddenly everywhere.
DHRUV64 has cleared the most important hurdle: it has moved from theoretical to fabricated silicon. The chip exists. It boots Linux. It passes validation. The processor pipeline behind it — THEJAS to DHRUV to Dhanush — is continuous, funded, and government-backed at an unprecedented scale.
The remaining challenges — commercial adoption, software ecosystem maturity, domestic fabrication at advanced nodes — are engineering problems. Engineering problems have engineering solutions. The dependency problem that DHRUV64 solves is a sovereignty problem. Sovereignty problems do not have engineering solutions. They require exactly what India has now built: architecture ownership, institutional continuity, and the political will to sustain both.
In an era where computing power defines strategic strength, DHRUV64 is India's declaration that it will own its silicon future — not lease it. From this chip to the Dhanush series and beyond, the country is building something more enduring than a processor: a lineage.
